1. Field of the Invention
The present invention generally relates to integrated circuit devices and, more particularly to delay locked loops utilized in integrated circuit devices.
2. Description of the Related Art
Delay locked loops (DLL) are utilized in a wide variety of integrated circuit (IC) devices to synchronize output signals with periodic input signals. In other words, the objective of the DLL is to adjust a phase difference between the input and output signals near zero, for example, to align rising or falling edges of the input and output signals.
FIG. 1 illustrates an exemplary dynamic random access memory (DRAM) device 200 utilizing a delay locked loop (DLL) circuit 100. A typical requirement of DRAM specifications is that data from memory arrays 204 be available on output lines DQ[0:N] in conjunction with the rising edge (and falling edge in double data rate devices) of an externally supplied clock signal (EXT CLK). In some cases, the DRAM 200 may supply a data strobe signal DQS controlled, for example by DQS generator 206. Typically, the DQS signal should also be synchronized with EXT CLK, thus indicating the data is available.
The DLL circuit 100 may be used to synchronize the DQS and DQ signals with the EXT CLK signal through the introduction of an artificial delay of EXT CLK. Thus, the DLL circuit 100 may be used to increase the valid output data window by synchronizing the output of data with both the rising and falling edges of an output clock CLKOUT applied to the driver circuits 208.
As illustrated, the DLL circuit 100 generally includes a phase blender circuit 102, a coarse adjust circuit 104, a counter 106, and a phase detector 108.
The EXT CLK may pass through one or more electrical connections and circuits before being received by the DLL circuit 100 as the CLKIN signal. The CLKIN signal may pass through the phase blender circuit 102 (also referred to as the fine adjust circuit). The output of the phase blender circuit (CLKIN—BLENDED) may then pass through the coarse adjust circuit 104 before being output as a CLKOUT signal. The CLKOUT signal may pass through one or more electrical connections and circuits before being externally output as a data strobe signal, DQS.
The phase detector 108 may be used to synchronize the externally received clock signal with DQS by comparing the CLKIN signal to a feedback clock signal CLKFB signal using feedback loop 112. The feedback clock signal CLKFB may be produced by a feedback delay 110 which may be inserted into the feedback loop 112 to mimic any delay between the externally used clock signals (EXT CLK and DQS) and the internal clock signals CLKIN and CLKOUT created by the electrical connections and circuits external to the DLL circuit 100. By mimicking delays in such external circuitry, EXT CLK and DQS may be more accurately synchronized.
To synchronize the CLKIN and CLKFB signals, the phase detector 108 may compare the phase of CLKFB to CLKIN and generate a signal to the counter 106. The counter 106 may output control signals which may be used to align the phases of CLKIN and CLKFB. The counter 106 may adjust both of the control signals based on the phase difference detected by the phase detector 108.
The counter 106 may use adjustments to the control signal for the phase blender circuit 102 to make relatively small adjustments to the phase of CLKOUT, and/or make adjustments to the output signal to the coarse adjust circuit 104 to make relatively large adjustments to the phase of CLKOUT. The coarse adjust circuit 104 may contain several delay elements which may be selectively enabled (the combination of delay elements is referred to as a delay line). By varying the number of enabled delay elements, the coarse adjust circuit 104 may make large incremental adjustments to the phase of CLKOUT. The combined adjustments of the coarse adjust circuit 104 and the phase blender circuit 102 may allow for large, accurate adjustments in the phase of the CLKOUT signal.
In some cases, the control signals output by the counter may be in the form of a count (e.g., 7.8). One signal from the counter 106 (e.g., the integer portion of the count, 7) may control the coarse adjust circuit 104 and another signal from the counter 106 (e.g., the decimal portion of the count, 0.8) may control the phase blender circuit 102. Each time the counter 106 issues new control signals for the phase blender circuit 102 and the coarse adjust circuit 104, the control signals may be latched by a blender latch 210 and a coarse adjust latch 212 in order to preserve the control signals for use by the phase blender circuit 102 and the coarse adjust circuit 104 for use with a current clock signal being processed. Each latch 210, 212 may only latch a single control signal.
As a given clock edge of CLKIN moves through the phase blender circuit 102 and the coarse adjust circuit 104, it may be delayed, for example, by the delay line in the coarse adjust circuit 104. In some cases, the delay line may delay the CLKOUT signal from the CLKIN signal by one or more multiples of their clock periods. In some cases, the delay caused by the delay line may cause errors in applying the fine adjust and coarse adjust settings.
For example, the CLKIN signal may be delayed over one clock cycle as it passes through the coarse adjust circuit 104. Because the CLKIN signal is delayed just over one clock cycle, each CLKOUT cycle may reflect the present coarse adjust setting but the previous phase blender setting. Thus, during a first clock cycle, the counter may adjust the count to 9.9 and during a second clock cycle the counter may adjust the count to 10.0. The adjustment may be made, for example, in response to a changing operating temperature and/or voltage or due to a change in the external signal EXT CLK.
As the CLKIN signal passes through the DLL circuit 100, the blender adjustment made to the signal may be 0.9 (from the blender setting during the first clock cycle), and due to the delay of over a cycle in the coarse adjust circuit 104, the coarse adjustment made to CLKOUT may be 10 (from the coarse adjust setting during the second clock cycle). Accordingly, the CLKOUT adjustment may be 10.9, a setting which differs from the desired adjustments of 9.9 during the first clock cycle and 10.0 during the second clock cycle. Similarly, if the counter control setting during a first clock cycle is 7.0 and the counter control setting during a second clock cycle is 6.9, the adjustment made to CLKOUT may be the undesired adjustment of 6.0.
To prevent such undesired adjustments, current methods of applying DLL control signals may employ delay elements arranged in different configurations. In some cases, those configurations may result in high complexity, large layout sizes, high power consumption, or frequency limits of a DLL circuit. Accordingly, there is a need for improved techniques and circuit configurations for synchronously applying control signals in a DLL circuit.